Pong FPGA Nexys 2

Pong FPGA Nexys 2

Pong

Pong japones es un juego de deportes en dos dimensiones que simula un tenis de mesa. El jugador controla en el juego una paleta moviéndola verticalmente en la parte izquierda de la pantalla, y puede competir tanto contra un oponente controlado por computadora, como con otro jugador humano que controla una segunda paleta en la parte opuesta. Los jugadores pueden usar las paletas para pegarle a la pelota hacia un lado u otro. El objetivo consiste en que uno de los jugadores consiga más puntos que el oponente al finalizar el juego. Estos puntos se obtienen cuando el jugador adversario falla al devolver la pelota. 1

Pong.png

Diseño del Proyecto

Para realizar el proyecto se necesita principalmente de:

Tarjeta FPGA

Una Tarjeta FPGA Nexys 2 es usada para realizar el juego. El hardware es descrito y sintetizado en Verilog

NEXYS2_400.jpg

La resolución de salida es 640x480 pixeles, utilizando el puerto VGA de la tarjeta.

Posicionamiento Espacial

La posición de la paleta y la bola esta definidos desde el origen del sistema coordenado. El origen entonces es, la esquina superior izquierda. Este es el punto de referencia para el juego y el display en general. Los objetos se definen a partir del origen, su altura y anchura. Por ejemplo, la bola tiene dimensión de 10x10 pixeles.
El eje horizontal es llamado HMAX, y el vertical VMAX.

Vector.png

Limitaciones del Diseño

La bola se mueve en dirección H y V por medio de adición vectorial. Se mueve aleatoriamente, logrando tener 28 diferentes combinaciones de vectores aleatorios.
Las paletas solo se pueden mover en el eje vertical y no se salen del margen establecido.
Si la bola toca el limite superior o inferior, se niega la componente y del vector de movimiento, con esto se logra el rebote. Establecido así:
RIGHT 1'b0
LEFT 1'b1
DOWN 1'b0
UP 1'b1
si BALL <= UP, BALL = DOWN
Si la bola toca las paletas, se niegan ambos vectores de movimiento, aplicando la misma lógica anterior, la bola rebota de la paleta.
Si la bola toca alguno de los limites horizontales, la bola deberá reaparecer en el centro de la pantalla y marcar un punto al lado contrario de donde "atraveso" la bola.

Puerto VGA

Vga_1.png

El puerto VGA utiliza básicamente 5 cables. Tres de ellos se emplean para describir el color(Rojo,Verde,Azul en ingles RGB) y los otros 2 se utilizan para sincronizar el haz de electrones con el monitor(Sincronización vertical y horizontal, en ingles H-Sync, V-Synch). El haz de electrones se desplaza linea por linea desde la esquina superior izquierda a la inferior derecha mientras muestra los pixeles en la pantalla. El color varia en paralelo al movimiento.
Los colores esta limitados a 8 bits en la tarjeta Nexys 2. Entonces hay 3 bits para rojo, 3 para verde, y 2 para azul.

Se tendrá entonces un diagrama para el control vga así:

Vgadriver.png

Al final, el circuito exclusivamente del sistema VGA se vera así:

Screen%20Shot%202015-05-20%20at%208.19.30%20PM.png

Diseño Lógico

El sistema, en esencia es tiene un diseño lógico sencillo. Tiene dos paletas, y cuatro pulsadores, el sistema refrescara cada poseedge del clk el dato del pulsador recibido y mover la paleta. Entonces si la bola choca con la pelota rebotara.

CapturaFin.JPG

Diagrama de Bloques Programa Xilinx Ise

PONG.jpg

Diagrama de Flujo

Implementación

Con esto en mente, se puede realizar el modelado en la plataforma Xilinx ISE, usando el lenguaje de descripción de hardware, Verilog.
Se tendrán entonces 6 Módulos, así:

Modulo Top

Realiza la conexión entre señales de entrada y salida con los submódulos de procesamiento.
Hace el llamado a las señales de entrada clk, para utilizar la frecuencia de sincronizacion.
reset, se establece como switch que resetea el sistema.
sw, seran los 3 swiches que se utilizan en el modulo de color, para cambiar el color que muestra la pantalla vga.
puls1,2,3,4 seran los pulsadores que moveran las paletas, 1 y 2 para la izquierda, 3 y 4 para la derecha.
hsync, vsync, son las salidas predeterminadas para la visualizacion vga
rgb de 3 bits seran los colores, como se explica en el modulo colores.

Código Top
module top_vga(
    input clk, reset,
    input [2:0]sw,
    input puls1,
    input puls2,
    input puls3,
    input puls4,
    output hsync, vsync,
    output [2:0] rgb
    );
 
    wire [9:0] w_posbarrady;
    wire [9:0] w_posbarraiy;
    wire [2:0] w_sw2;
    wire [9:0] w_posx;
    wire [9:0] w_posy;
 
    position posicion(.clk(clk), .posx(w_posx), .posy(w_posy), .posbarraiy(w_posbarraiy), .posbarrady(w_posbarrady));
    color colores(.clk(clk),.sw2(w_sw2));
    Barrad barrad(.clk(clk), .puls3(puls3), .puls4(puls4), .posbarrady(w_posbarrady));
    Barrai barrai(.clk(clk), .puls1(puls1), .puls2(puls2), .posbarraiy(w_posbarraiy));
    Imagen image(.clk(clk), .reset(reset),.sw(sw),.sw2(w_sw2), .hsync(hsync), .vsync(vsync),.rgb(rgb), 
    .posx(w_posx), .posy(w_posy), .posbarrady(w_posbarrady), .posbarraiy(w_posbarraiy));
endmodule

Modulo VGA

Recibe las señales de color y posición para dibujar las paletas, la bola, y el margen, refrescando a la frecuencia del clk.
Se realiza en mismo llamado de clk y reset para que sincronice y resetee el sistema.
posx y posy, seran las posiciones del vector de la pelota, con estos mismos se dibuja la pelota de tamaño 12x12.
posbarraiy, posbarrady, al igual que la pelota, seran las posiciones, en las que, en el eje X seran el mismo, mientras que en el eje Y cambiara, se tiene con tamaño de 10x100

Código VGA
module Imagen( 
    input clk, reset, 
    input [9:0]posx, 
    input [9:0]posy,
    input [2:0]sw,
    input [2:0]sw2, 
    input [9:0]posbarraiy,
    input [9:0]posbarrady,
    output hsync, vsync,
    output [2:0] rgb
    );
    //signal declaration
    reg [2:0] rgb_reg;
    wire video_on;
     wire [9:0] x,y;
 
    //instantiate vga sync circuit
    vga_sync vsync_unit (.clk(clk), .reset(reset), .hsync(hsync), . vsync(vsync), .video_on(video_on), . p_tick(), .pixel_x(x), .pixel_y(y));
 
    //rgb buffer
     always @(posedge clk, posedge reset) begin
        if (reset) rgb_reg <= 0;
        else begin
            if (x>posx & x<(12+posx) & y>posy & y<(12+posy)) rgb_reg<=3'b111;
            else if (x>=0 & x<=10 & y>=0 & y<=480) rgb_reg<=3'b111;
            else if (x>=630 & x<=640 & y>=0 & y<=480) rgb_reg<=3'b111;
            else if (x>=0 & x<=640 & y>=0 & y<=10) rgb_reg<=3'b111;
            else if (x>=0 & x<=640 & y>=470 & y<=480) rgb_reg<=3'b111;
            else if (y>=posbarraiy & y<=(100+posbarraiy) & x>=30 & x<=40) rgb_reg<=3'b111;
            else if (y>=posbarrady & y<=(100+posbarrady) & x>=600 & x<=610) rgb_reg<=3'b111;
            else rgb_reg <= sw;
        end
    end
 
    // output
    assign rgb = (video_on) ? rgb_reg : 3'b000;
endmodule

y el submódulo del circuito vga donde se establece el tamaño del display, 640x480, tambien el dibujado de pixeles.

Submodulo VGA:
module vga_sync(
    input clk, reset,
    output hsync , vsync , video_on, p_tick,
    output [9:0] pixel_x, pixel_y
    );
 
    //constant declaration
    //VGA 640-by-480 sync parameters
 
    localparam HD = 640;     // horizontal display area
    localparam HF = 48 ;     // h.front(left)border
    localparam HB = 16 ;     // h.back(right)border
    localparam HR = 96 ;     // h.retrace
    localparam VD = 480;     // vertical display area
    localparam VF = 10;         // v.front(top)border
    localparam VB = 33;         // v.back(bottom)border
    localparam VR = 2;        // v.retrace
 
    // mod-2 counter
 
    reg mod2_reg;
    wire mod2_next ;
    // sync counters
    reg [9:0] h_count_reg, h_count_next;
    reg [9:0] v_count_reg , v_count_next;
    // output buffer
    reg v_sync_reg , h_sync_reg;
    wire v_sync_next , h_sync_next ;
 
    // status signal
    wire h_end, v_end, pixel_tick;
 
    // body
    // registers
 
    always @(posedge clk, posedge reset)
        if (reset)begin 
            mod2_reg <= 1'b0;
            v_count_reg <= 0;
            h_count_reg <= 0;
            v_sync_reg <= 1'b0;
            h_sync_reg <= 1'b0;
        end
        else begin
            mod2_reg <= mod2_next;
            v_count_reg <= v_count_next;
            h_count_reg <= h_count_next;
            v_sync_reg <= v_sync_next;
            h_sync_reg <= h_sync_next;
        end
 
    // mod-2 circuit to generate 25 MHz enable tick
    assign mod2_next = ~mod2_reg;
    assign pixel_tick = mod2_reg;
 
    // status signals
    // end of horizontal counter (799)
    assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
    // end of vertical counter (524)
    assign v_end = (v_count_reg==(VD+VF+VB+VR-1));
 
    // next-state logic of mod-800 horizontal sync counter
    always @*
        if (pixel_tick)
        // 25 MHz p u l s e
            if (h_end)
                h_count_next = 0;
            else
                h_count_next = h_count_reg+1;
        else
            h_count_next = h_count_reg;
 
    // next-state logico fmod-525 vertical sync counter
    always @*
        if (pixel_tick & h_end)
            if (v_end)
                v_count_next = 0 ;
            else
                v_count_next = v_count_reg + 1;
        else
            v_count_next = v_count_reg;
 
    // horizontal and vertical sync, buffered to avoid glitch
    // h-sync-next asserted between 656 and 751
    assign h_sync_next = (h_count_reg>=(HD+HB) && h_count_reg<=(HD+HB+HR-1));
    // vh-sync-next asserted between 490 and 491
    assign v_sync_next = (v_count_reg>=(VD+VB) && v_count_reg<=(VD+VB+VR-1));
    // video on/off
    assign video_on = (h_count_reg<HD) && (v_count_reg<VD);
    // output
    assign hsync = h_sync_reg;
    assign vsync = v_sync_reg;
    assign pixel_x = h_count_reg;
    assign pixel_y = v_count_reg;
    assign p_tick = pixel_tick;
endmodule

Modulo Paletas

Recibe la señal de los pulsadores para re-dibujar la paleta conforme a la posición cambiante, y enviar esto al modulo de muestreo.
En este caso se muestra el código de la paleta derecha, que como se menciona antes, utiliza los pulsadores 3 y 4.
El código resume en que cuando se presione el pulsador 3, se reste a la posición de la barra en el eje Y logrando que se mueva hacia arriba, y que, cuando se pulse el pulsador 4, que le sume la posición, moviendo la paleta hacia abajo.

Código Paletas
module Barrad(puls3, puls4, clk, posbarrady);
 
    input clk;
    input puls3;
    input puls4;
    output reg [9:0] posbarrady=60;
 
    reg clk3;
    reg [16:0] temp1=0;
    always @(posedge clk) begin
        temp1=temp1+1;
        clk3=temp1[16];
    end
 
    always@(posedge clk3)begin
 
        if(puls3)begin
            posbarrady=posbarrady-1;
            if (posbarrady<=10) posbarrady=10;
            else posbarrady=posbarrady;          
            end
        else if(puls4)begin
            posbarrady=posbarrady+1;
            if (posbarrady>=470) posbarrady=470;
            else posbarrady=posbarrady;
            end
        else posbarrady=posbarrady;
    end
 
endmodule

Modulo Pelota

Recibe la posición de la pelota, y la hace cambiar de dirección cuando la posición de esta este igualada a la de los márgenes, o bien las paletas. Realizando así la animación de rebote.
Recibe la posición de la pelota, y de las barras. La pelota rebotara en cuanto se cumpla alguna de las condiciones de posición, así:
dirx=0, diry=0: Esto se traduce cuando la pelota se mueve en direccion diagonal abajo derecha. Y que cuando llegue las posiciones, de bien las margenes o, las barras, que cambie la direccion a dirx=1 si toca el borde lateral derecho, o dirx=0 si toca el lateral izquierdo. diry=1 si toca el borde superior, o diry=0 si toca el inferior.
Las mismas condiciones reciben las otras tres formas de choque, asi:
dirx=1, diry=0 -> dirx=0 Choque margen lateral d, dirx=1, lateral izq. diry=0 inferior, diry=1 superior.
dirx=0, diry=1 -> dirx=1 Choque margen lateral d, dirx=0, lateral izq. diry=1 inferior, diry=0 superior.
dirx=1, diry=1 -> dirx=0 Choque margen lateral d, dirx=1, lateral izq. diry=0 inferior, diry=1 superior.

Código Pelota
module position(clk, posx, posy, posbarraiy, posbarrady);
    input clk;
    input [9:0] posbarraiy;
    input [9:0] posbarrady;
    output reg [9:0] posx=600;
    output reg [9:0] posy=400;
 
    reg clk2;
    reg [18:0] temp=0;
    reg dirx=0;
    reg diry=0;
    always @(posedge clk) begin
        temp=temp+1;
        clk2=temp[18];
    end
 
    always @(posedge clk2) begin
 
        // Golpea diagonal abajo derecha
        if (dirx==0 & diry==0) begin
            posx=posx+1;
            posy=posy+1;
            if (posx>=610) dirx=1;
            else dirx=0;
            if (posy>=450) diry=1;
            else diry=0;
 
            // Golpe Con la Paleta
            if(posx>=30 & posx<=40 & posx>=posbarraiy & posx<=posbarraiy+100) 
            begin
            dirx=1;
            diry=0;
            end
            else if(posx>=610 & posx<=600 & posx>=posbarrady & posx<=posbarrady+100)
            begin
            dirx=1;
            diry=0;
            end
        end
 
        else if (dirx==1 & diry==0) begin
            posx=posx-1;
            posy=posy+1;
            if (posx<=10) dirx=0;
            else dirx=1;
            if (posy>=450) diry=1;
            else diry=0;
 
            if(posx>=30 & posx<=40 & posx>=posbarraiy & posx<=posbarraiy+100) 
            begin
            dirx=0;
            diry=1;
            end
            else if(posx>=610 & posx<=600 & posx>=posbarrady & posx<=posbarrady+100)
            begin
            dirx=0;
            diry=1;
            end
 
        end
        else if (dirx==0 & diry==1) begin
            posx=posx+1;
            posy=posy-1;
            if (posx>=610) dirx=1;
            else dirx=0;
            if (posy<=10) diry=0;
            else diry=1;
 
            if(posx>=30 & posx<=40 & posx>=posbarraiy & posx<=posbarraiy+100) 
            begin
            dirx=1;
            diry=0;
            end
            else if(posx>=610 & posx<=600 & posx>=posbarrady & posx<=posbarrady+100)
            begin
            dirx=0;
            diry=1;
            end
 
        end
        if (dirx==1 & diry==1) begin
            posx=posx-1;
            posy=posy-1;
            if (posx<=10) dirx=0;
            else dirx=1;
            if (posy<=10) diry=0;
            else diry=1;
 
            if(posx>=30 & posx<=40 & posx>=posbarraiy & posx<=posbarraiy+100) 
            begin
            dirx=0;
            diry=1;
            end
            else if(posx>=610 & posx<=600 & posx>=posbarrady & posx<=posbarrady+100)
            begin
            dirx=0;
            diry=1;
            end
        end        
    end
 
endmodule

Modulo Color:

Establece una relacion entre 3 bits, y R-G-B, para lograr diferentes combinaciones basicas a mostrar asi:
000 -> Negro
111 -> Blanco
100 -> Rojo
010 -> Verde
001 -> Azul
110 -> Rojo 50% - Verde 50% - Azul 0%
011 -> Rojo 0% - Verde 50% - Azul 50%
101 -> Rojo 50% - Verde 0% - Azul 50%

Modulo Control

En este modulo se controla la posición de la pelota respecto a los choques, para aumentar una variable cada vez que la pelota toca el margen; Este valor se dirigira al modulo Acumulador.
Es decir, este modulo cuenta cada vez que toca el margen para enviar un bit al acumulador.

Código Control
module Control(clk2, posx, count1, count2);
     input [9:0]posx; 
     input clk2;
     output reg count1;
     output reg count2;
 
    reg [3:0]next_state;
    reg [3:0]current_state;
 
    parameter inicio=0, i1=1, d1=2;
    always@(posx or current_state) begin
    case (current_state)
 
        inicio: begin
                        count1=0;
                        count2=0;
                        if (posx==10) next_state=i1;
                        else if (posx==620) next_state=d1;
                        else next_state=inicio;
                    end    
 
        i1: begin
                        count1=1;
                        count2=0;
                        next_state=inicio;
                    end                        
 
        d1: begin
                        count1=0;
                        count2=1;
                        next_state=inicio;
                    end            
 
                            default: begin
                                    count1=0;
                                    count2=0;
                                    next_state=inicio;
                            end
 
        endcase
        end
        always @(negedge clk2) begin
 
        current_state=next_state;
 
    end
 
endmodule

Modulo Acumulador

Se reciben los bits del modulo control, y los almacena en un registro, que se mostrara en el siete segmentos.

Código Acumulador
module Acumulador( unidades1, decenas1, unidades2, decenas2, count1, count2, clk2);
input count1; 
input count2; 
input clk2;
output reg [3:0] unidades2=0;
output reg [3:0] decenas2=0;
output reg [3:0] unidades1=0;
output reg [3:0] decenas1=0;
 
always @(posedge clk2) begin
   //Contador Unidades, Para en 9
    if ((count1==1)&&(unidades1<9)) unidades1=unidades1+1;
    //Contador Decenas, Para en 99
        else if ((count1==1)&&(decenas1==9)&&(unidades1==9)) begin
    decenas1 = 9;
    unidades1= 9;
        end
    else if((count1==1)&&(unidades1==9)) begin  
 
        decenas1=decenas1+1; 
        unidades1=0; 
    end
 
    if ((count2==1)&&(unidades2<9)) unidades2=unidades2+1;
    //Contador Decenas, Para en 99
        else if ((count2==1)&&(decenas2==9)&&(unidades2==9)) begin
    decenas2 = 9;
    unidades2= 9;
        end
    else if((count2==1)&&(unidades2==9)) begin  
 
        decenas2=decenas2+1; 
        unidades2=0; 
    end
    end
 
endmodule

Modulo Siete Segmentos

Recibe los datos del control y acumulador y los muestra en el panel siete segmentos de la tarjeta.

Código Siete Segmentos
module Sieteseg(unidades1, decenas1,unidades2, decenas2,salidas, an,clk);
 
input [3:0]unidades2;
input [3:0]decenas2;
input [3:0]unidades1;
input [3:0]decenas1;
input  clk;
output reg [6:0]salidas;
output reg [3:0]an=4'b1110;
reg [3:0]display;
reg [16:0]temp=0;
reg clk2=0;
 
always @(posedge clk)begin
temp=temp+1;
clk2=temp[16];
end
 
always @(posedge clk2) begin
 
if(an==4'b1110) begin
    display=decenas1; 
    an=4'b1101;
end    
else if (an==4'b1101) begin 
    display=unidades2; 
    an=4'b1011; 
end
else if(an==4'b1011) begin
    display=decenas2; 
    an=4'b0111;
end    
else if (an==4'b0111) begin 
    display=unidades1;
    an=4'b1110; 
end
else begin 
display=display;
an=4'b0000;
end
 
end
 
always @(display)begin
 
case(display) 
 
//             abcdefg     
0:salidas = 7'b1000000; 
1:salidas= 7'b1111001;
2:salidas= 7'b0100100;
3:salidas= 7'b0110000;
4:salidas=7'b0011001;
5:salidas= 7'b0010010;
6:salidas= 7'b0000010;
7:salidas=7'b1111000;
8:salidas=7'b0000000;
9:salidas= 7'b0010000;
default: salidas=7'b1111111;
 
endcase
end
endmodule

UCF

## This file is a general .ucf for Nexys2 rev A board
## To use it in a project:
## - remove or comment the lines corresponding to unused pins
## - rename the used signals according to the project
 
## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
## Both versions are provided in this file.
## Keep only the appropriate one, and remove or comment the other one.
 
## Clock pin for Nexys 2 Board
NET "clk"         LOC = "B8";    # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK,                 Sch name = GCLK0
#NET "clk1"        LOC = "U9";    # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK,        Sch name = GCLK1
 
## onBoard USB controller
## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
 
## Data bus for both the DEPP and DSTM interfaces uncomment lines 20-27 if using either one
#NET "DB<0>"       LOC = "R14";   # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL,                   Sch name = U-FD0
#NET "DB<1>"       LOC = "R13";   # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL,                   Sch name = U-FD1
#NET "DB<2>"       LOC = "P13";   # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL,                   Sch name = U-FD2
#NET "DB<3>"       LOC = "T12";   # Bank = 2, Pin name = IO_L20P_2, Type = I/O,                        Sch name = U-FD3
#NET "DB<4>"       LOC = "N11";   # Bank = 2, Pin name = IO_L18N_2, Type = I/O,                        Sch name = U-FD4
#NET "DB<5>"       LOC = "R11";   # Bank = 2, Pin name = IO, Type = I/O,                               Sch name = U-FD5
#NET "DB<6>"       LOC = "P10";   # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK,         Sch name = U-FD6
#NET "DB<7>"       LOC = "R10";   # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK,         Sch name = U-FD7
 
## If using the DEPP interface uncomment lines 30-33
#NET "EppWRITE"    LOC = "V16";   # Bank = 2, Pin name = IP, Type = INPUT,                             Sch name = U-FLAGC
#NET "EppASTB"     LOC = "V14";   # Bank = 2, Pin name = IP_L23P_2, Type = INPUT,                      Sch name = U-FLAGA
#NET "EppDSTB"     LOC = "U14";   # Bank = 2, Pin name = IP_L23N_2, Type = INPUT,                      Sch name = U-FLAGB
#NET "EppWAIT"     LOC = "N9";    # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK,        Sch name = U-SLRD
 
## If using the DSTM interface uncomment lines 36-45
#NET "DstmIFCLK"   LOC = "T15";   # Bank = 2, Pin name = IO/VREF_2, Type = VREF,                       Sch name = U-IFCLK
#NET "DstmSLCS"    LOC = "T16";   # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL,               Sch name = U-SLCS
#NET "DstmFLAGA"   LOC = "V14";   # Bank = 2, Pin name = IP_L23P_2, Type = INPUT,                      Sch name = U-FLAGA
#NET "DstmFLAGB"   LOC = "U14";   # Bank = 2, Pin name = IP_L23N_2, Type = INPUT,                      Sch name = U-FLAGB
#NET "DstmADR<0>"  LOC = "T14";   # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL,                   Sch name = U-FIFOAD0
#NET "DstmADR<1>"  LOC = "V13";   # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF,                Sch name = U-FIFOAD1
#NET "DstmSLRD"    LOC = "N9";    # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK,        Sch name = U-SLRD
#NET "DstmSLWR"    LOC = "V9";    # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK,        Sch name = U-SLWR
#NET "DstmSLOE"    LOC = "V15";   # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL,               Sch name = U-SLOE
#NET "DstmPKTEND"  LOC = "V12";   # Bank = 2, Pin name = IO_L19P_2, Type = I/O,                        Sch name = U-PKTEND
 
#NET "UsbMode"     LOC = "U15";   # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL,               Sch name = U-INT0#
#NET "UsbRdy"      LOC = "U13";   # Bank = 2, Pin name = IP, Type = INPUT,                             Sch name = U-RDY
 
## onBoard Cellular RAM and StrataFlash
#NET "MemOE"       LOC = "T2";    # Bank = 3, Pin name = IO_L24P_3, Type = I/O,                        Sch name = OE
#NET "MemWR"       LOC = "N7";    # Bank = 2, Pin name = IO_L07P_2, Type = I/O,                        Sch name = WE
 
#NET "RamAdv"      LOC = "J4";    # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK,               Sch name = MT-ADV
#NET "RamCS"       LOC = "R6";    # Bank = 2, Pin name = IO_L05P_2, Type = I/O,                        Sch name = MT-CE
#NET "RamClk"      LOC = "H5";    # Bank = 3, Pin name = IO_L08N_3, Type = I/O,                        Sch name = MT-CLK
#NET "RamCRE"      LOC = "P7";    # Bank = 2, Pin name = IO_L07N_2, Type = I/O,                        Sch name = MT-CRE
#NET "RamLB"       LOC = "K5";    # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK,               Sch name = MT-LB
#NET "RamUB"       LOC = "K4";    # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK,               Sch name = MT-UB
#NET "RamWait"     LOC = "F5";    # Bank = 3, Pin name = IP, Type = INPUT,                             Sch name = MT-WAIT
 
#NET "FlashRp"     LOC = "T5";    # Bank = 2, Pin name = IO_L04N_2, Type = I/O,                        Sch name = RP#
#NET "FlashCS"     LOC = "R5";    # Bank = 2, Pin name = IO_L04P_2, Type = I/O,                        Sch name = ST-CE
#NET "FlashStSts"  LOC = "D3";    # Bank = 3, Pin name = IP, Type = INPUT,                             Sch name = ST-STS
 
#NET "MemAdr<1>"   LOC = "J1";    # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK,               Sch name = ADR1
#NET "MemAdr<2>"   LOC = "J2";    # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK,         Sch name = ADR2
#NET "MemAdr<3>"   LOC = "H4";    # Bank = 3, Pin name = IO_L09P_3, Type = I/O,                        Sch name = ADR3
#NET "MemAdr<4>"   LOC = "H1";    # Bank = 3, Pin name = IO_L10N_3, Type = I/O,                        Sch name = ADR4
#NET "MemAdr<5>"   LOC = "H2";    # Bank = 3, Pin name = IO_L10P_3, Type = I/O,                        Sch name = ADR5
#NET "MemAdr<6>"   LOC = "J5";    # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK,               Sch name = ADR6
#NET "MemAdr<7>"   LOC = "H3";    # Bank = 3, Pin name = IO_L09N_3, Type = I/O,                        Sch name = ADR7
#NET "MemAdr<8>"   LOC = "H6";    # Bank = 3, Pin name = IO_L08P_3, Type = I/O,                        Sch name = ADR8
#NET "MemAdr<9>"   LOC = "F1";    # Bank = 3, Pin name = IO_L05P_3, Type = I/O,                        Sch name = ADR9
#NET "MemAdr<10>"  LOC = "G3";    # Bank = 3, Pin name = IO_L06P_3, Type = I/O,                        Sch name = ADR10
#NET "MemAdr<11>"  LOC = "G6";    # Bank = 3, Pin name = IO_L07P_3, Type = I/O,                        Sch name = ADR11
#NET "MemAdr<12>"  LOC = "G5";    # Bank = 3, Pin name = IO_L07N_3, Type = I/O,                        Sch name = ADR12
#NET "MemAdr<13>"  LOC = "G4";    # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF,                Sch name = ADR13
#NET "MemAdr<14>"  LOC = "F2";    # Bank = 3, Pin name = IO_L05N_3, Type = I/O,                        Sch name = ADR14
#NET "MemAdr<15>"  LOC = "E1";    # Bank = 3, Pin name = IO_L03N_3, Type = I/O,                        Sch name = ADR15
#NET "MemAdr<16>"  LOC = "M5";    # Bank = 3, Pin name = IO_L19P_3, Type = I/O,                        Sch name = ADR16
#NET "MemAdr<17>"  LOC = "E2";    # Bank = 3, Pin name = IO_L03P_3, Type = I/O,                        Sch name = ADR17
#NET "MemAdr<18>"  LOC = "C2";    # Bank = 3, Pin name = IO_L01N_3, Type = I/O,                        Sch name = ADR18
#NET "MemAdr<19>"  LOC = "C1";    # Bank = 3, Pin name = IO_L01P_3, Type = I/O,                        Sch name = ADR19
#NET "MemAdr<20>"  LOC = "D2";    # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF,                Sch name = ADR20
#NET "MemAdr<21>"  LOC = "K3";    # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK,         Sch name = ADR21
#NET "MemAdr<22>"  LOC = "D1";    # Bank = 3, Pin name = IO_L02P_3, Type = I/O,                        Sch name = ADR22
#NET "MemAdr<23>"  LOC = "K6";    # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK,               Sch name = ADR23
 
#NET "MemDB<0>"    LOC = "L1";    # Bank = 3, Pin name = IO_L15P_3, Type = I/O,                        Sch name = DB0
#NET "MemDB<1>"    LOC = "L4";    # Bank = 3, Pin name = IO_L16N_3, Type = I/O,                        Sch name = DB1
#NET "MemDB<2>"    LOC = "L6";    # Bank = 3, Pin name = IO_L17P_3, Type = I/O,                        Sch name = DB2
#NET "MemDB<3>"    LOC = "M4";    # Bank = 3, Pin name = IO_L18P_3, Type = I/O,                        Sch name = DB3
#NET "MemDB<4>"    LOC = "N5";    # Bank = 3, Pin name = IO_L20N_3, Type = I/O,                        Sch name = DB4
#NET "MemDB<5>"    LOC = "P1";    # Bank = 3, Pin name = IO_L21N_3, Type = I/O,                        Sch name = DB5
#NET "MemDB<6>"    LOC = "P2";    # Bank = 3, Pin name = IO_L21P_3, Type = I/O,                        Sch name = DB6
#NET "MemDB<7>"    LOC = "R2";    # Bank = 3, Pin name = IO_L23N_3, Type = I/O,                        Sch name = DB7
#NET "MemDB<8>"    LOC = "L3";    # Bank = 3, Pin name = IO_L16P_3, Type = I/O,                        Sch name = DB8
#NET "MemDB<9>"    LOC = "L5";    # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF,                Sch name = DB9
#NET "MemDB<10>"   LOC = "M3";    # Bank = 3, Pin name = IO_L18N_3, Type = I/O,                        Sch name = DB10
#NET "MemDB<11>"   LOC = "M6";    # Bank = 3, Pin name = IO_L19N_3, Type = I/O,                        Sch name = DB11
#NET "MemDB<12>"   LOC = "L2";    # Bank = 3, Pin name = IO_L15N_3, Type = I/O,                        Sch name = DB12
#NET "MemDB<13>"   LOC = "N4";    # Bank = 3, Pin name = IO_L20P_3, Type = I/O,                        Sch name = DB13
#NET "MemDB<14>"   LOC = "R3";    # Bank = 3, Pin name = IO_L23P_3, Type = I/O,                        Sch name = DB14
#NET "MemDB<15>"   LOC = "T1";    # Bank = 3, Pin name = IO_L24N_3, Type = I/O,                        Sch name = DB15
 
## 7 segment display
NET "salidas<0>"      LOC = "L18";   # Bank = 1, Pin name = IO_L10P_1, Type = I/O,                        Sch name = CA
NET "salidas<1>"      LOC = "F18";   # Bank = 1, Pin name = IO_L19P_1, Type = I/O,                        Sch name = CB
NET "salidas<2>"      LOC = "D17";   # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL,                   Sch name = CC
NET "salidas<3>"      LOC = "D16";   # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL,                  Sch name = CD
NET "salidas<4>"      LOC = "G14";   # Bank = 1, Pin name = IO_L20P_1, Type = I/O,                        Sch name = CE
NET "salidas<5>"      LOC = "J17";   # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
NET "salidas<6>"      LOC = "H14";   # Bank = 1, Pin name = IO_L17P_1, Type = I/O,                        Sch name = CG
#NET "dp"          LOC = "C17";   # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL,                  Sch name = DP
 
NET "an<0>"       LOC = "F17";   # Bank = 1, Pin name = IO_L19N_1, Type = I/O,                        Sch name = AN0
NET "an<1>"       LOC = "H17";   # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL,                    Sch name = AN1
NET "an<2>"       LOC = "C18";   # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL,                  Sch name = AN2
NET "an<3>"       LOC = "F15";   # Bank = 1, Pin name = IO_L21P_1, Type = I/O,                        Sch name = AN3
 
## Leds
#NET "H_debug"      LOC = "J14";   # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL,       Sch name = JD10/LD0
#NET "V_debug"      LOC = "J15";   # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL,       Sch name = JD9/LD1
#NET "Led<2>"      LOC = "K15";   # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL,       Sch name = JD8/LD2
#NET "Led<3>"      LOC = "K14";   # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>"      LOC = "E17";   # Bank = 1, Pin name = IO, Type = I/O,                               Sch name = LD4? s3e500 only
#NET "Led<5>"      LOC = "P15";   # Bank = 1, Pin name = IO, Type = I/O,                               Sch name = LD5? s3e500 only
#NET "Led<6>"      LOC = "F4";    # Bank = 3, Pin name = IO, Type = I/O,                               Sch name = LD6? s3e500 only
#NET "Led<7>"      LOC = "R4";    # Bank = 3, Pin name = IO/VREF_3, Type = VREF,                       Sch name = LD7? s3e500 only
#NET "Led<4>"      LOC = "E16";   # Bank = 1, Pin name = N.C., Type = N.C.,                            Sch name = LD4? other than s3e500
#NET "Led<5>"      LOC = "P16";   # Bank = 1, Pin name = N.C., Type = N.C.,                            Sch name = LD5? other than s3e500
#NET "Led<6>"      LOC = "E4";    # Bank = 3, Pin name = N.C., Type = N.C.,                            Sch name = LD6? other than s3e500
#NET "Led<7>"      LOC = "P4";    # Bank = 3, Pin name = N.C., Type = N.C.,                            Sch name = LD7? other than s3e500
 
## Switches
NET "sw<0>"       LOC = "G18";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW0
NET "sw<1>"       LOC = "H18";   # Bank = 1, Pin name = IP/VREF_1, Type = VREF,                       Sch name = SW1
NET "sw<2>"       LOC = "K18";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW2
#NET "sw<3>"       LOC = "K17";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW3
#NET "sw<4>"       LOC = "L14";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW4
#NET "sw<5>"       LOC = "L13";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW5
#NET "sw<6>"       LOC = "N17";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW6
NET "reset"       LOC = "R17";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = SW7
 
## Buttons
NET "puls3"      LOC = "B18";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = BTN0
NET "puls4"      LOC = "D18";   # Bank = 1, Pin name = IP/VREF_1, Type = VREF,                       Sch name = BTN1
NET "puls1"      LOC = "E18";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = BTN2
NET "puls2"      LOC = "H13";   # Bank = 1, Pin name = IP, Type = INPUT,                             Sch name = BTN3
 
## VGA Connector 
NET "rgb<0>"   LOC = "R9";    # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
NET "rgb<0>"   LOC = "T8";    # Bank = 2, Pin name = IO_L10N_2, Type = I/O,                        Sch name = RED1
NET "rgb<0>" LOC = "R8";    # Bank = 2, Pin name = IO_L10P_2, Type = I/O,                        Sch name = RED2
#NET "G[0]" LOC = "N8";    # Bank = 2, Pin name = IO_L09N_2, Type = I/O,                        Sch name = GRN0
#NET "G[1]" LOC = "P8";    # Bank = 2, Pin name = IO_L09P_2, Type = I/O,                        Sch name = GRN1
NET "rgb<1>" LOC = "P6";    # Bank = 2, Pin name = IO_L05N_2, Type = I/O,                        Sch name = GRN2
#NET "B[0]" LOC = "U5";    # Bank = 2, Pin name = IO/VREF_2, Type = VREF,                       Sch name = BLU1
NET "rgb<2>" LOC = "U4";    # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL,             Sch name = BLU2
 
NET "hsync"    LOC = "T4";    # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL,            Sch name = HSYNC
NET "vsync"    LOC = "U3";    # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL,                 Sch name = VSYNC
 
## PS/2 connector
#NET "PS2C"        LOC = "R12";   # Bank = 2, Pin name = IO_L20N_2, Type = I/O,                        Sch name = PS2C
#NET "PS2D"        LOC = "P11";   # Bank = 2, Pin name = IO_L18P_2, Type = I/O,                        Sch name = PS2D
 
## FX2 connector
#NET "PIO<0>"      LOC = "B4";    # Bank = 0, Pin name = IO_L24N_0, Type = I/O,                        Sch name = R-IO1
#NET "PIO<1>"      LOC = "A4";    # Bank = 0, Pin name = IO_L24P_0, Type = I/O,                        Sch name = R-IO2
#NET "PIO<2>"      LOC = "C3";    # Bank = 0, Pin name = IO_L25P_0, Type = I/O,                        Sch name = R-IO3
#NET "PIO<3>"      LOC = "C4";    # Bank = 0, Pin name = IO, Type = I/O,                               Sch name = R-IO4
#NET "PIO<4>"      LOC = "B6";    # Bank = 0, Pin name = IO_L20P_0, Type = I/O,                        Sch name = R-IO5
#NET "PIO<5>"      LOC = "D5";    # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF,                Sch name = R-IO6
#NET "PIO<6>"      LOC = "C5";    # Bank = 0, Pin name = IO_L23P_0, Type = I/O,                        Sch name = R-IO7
#NET "PIO<7>"      LOC = "F7";    # Bank = 0, Pin name = IO_L19P_0, Type = I/O,                        Sch name = R-IO8
#NET "PIO<8>"      LOC = "E7";    # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF,                Sch name = R-IO9
#NET "PIO<9>"      LOC = "A6";    # Bank = 0, Pin name = IO_L20N_0, Type = I/O,                        Sch name = R-IO10
#NET "PIO<10>"     LOC = "C7";    # Bank = 0, Pin name = IO_L18P_0, Type = I/O,                        Sch name = R-IO11
#NET "PIO<11>"     LOC = "F8";    # Bank = 0, Pin name = IO_L17N_0, Type = I/O,                        Sch name = R-IO12
#NET "PIO<12>"     LOC = "D7";    # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF,                Sch name = R-IO13
#NET "PIO<13>"     LOC = "E8";    # Bank = 0, Pin name = IO_L17P_0, Type = I/O,                        Sch name = R-IO14
#NET "PIO<14>"     LOC = "E9";    # Bank = 0, Pin name = IO_L15P_0, Type = I/O,                        Sch name = R-IO15
#NET "PIO<15>"     LOC = "C9";    # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK,                Sch name = R-IO16
#NET "PIO<16>"     LOC = "A8";    # Bank = 0, Pin name = IO, Type = I/O,                               Sch name = R-IO17
#NET "PIO<17>"     LOC = "G9";    # Bank = 0, Pin name = IO, Type = I/O,                               Sch name = R-IO18
#NET "PIO<18>"     LOC = "F9";    # Bank = 0, Pin name = IO_L15N_0, Type = I/O,                        Sch name = R-IO19
#NET "PIO<19>"     LOC = "D10";   # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK,                 Sch name = R-IO20
#NET "PIO<20>"     LOC = "A10";   # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK,                 Sch name = R-IO21
#NET "PIO<21>"     LOC = "B10";   # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK,                 Sch name = R-IO22
#NET "PIO<22>"     LOC = "A11";   # Bank = 0, Pin name = IO, Type = I/O,                               Sch name = R-IO23
#NET "PIO<23>"     LOC = "D11";   # Bank = 0, Pin name = IO_L09N_0, Type = I/O,                        Sch name = R-IO24
#NET "PIO<24>"     LOC = "E10";   # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK,                 Sch name = R-IO25
#NET "PIO<25>"     LOC = "B11";   # Bank = 0, Pin name = IO/VREF_0, Type = VREF,                       Sch name = R-IO26
#NET "PIO<26>"     LOC = "C11";   # Bank = 0, Pin name = IO_L09P_0, Type = I/O,                        Sch name = R-IO27
#NET "PIO<27>"     LOC = "E11";   # Bank = 0, Pin name = IO_L08P_0, Type = I/O,                        Sch name = R-IO28
#NET "PIO<28>"     LOC = "F11";   # Bank = 0, Pin name = IO_L08N_0, Type = I/O,                        Sch name = R-IO29
#NET "PIO<29>"     LOC = "E12";   # Bank = 0, Pin name = IO_L06N_0, Type = I/O,                        Sch name = R-IO30
#NET "PIO<30>"     LOC = "F12";   # Bank = 0, Pin name = IO_L06P_0, Type = I/O,                        Sch name = R-IO31
#NET "PIO<31>"     LOC = "A13";   # Bank = 0, Pin name = IO_L05P_0, Type = I/O,                        Sch name = R-IO32
#NET "PIO<32>"     LOC = "B13";   # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF,                Sch name = R-IO33
#NET "PIO<33>"     LOC = "E13";   # Bank = 0, Pin name = IO, Type = I/O,                               Sch name = R-IO34
#NET "PIO<34>"     LOC = "A14";   # Bank = 0, Pin name = IO_L04N_0, Type = I/O,                        Sch name = R-IO35
#NET "PIO<35>"     LOC = "C14";   # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF,                Sch name = R-IO36
#NET "PIO<36>"     LOC = "D14";   # Bank = 0, Pin name = IO_L03P_0, Type = I/O,                        Sch name = R-IO37
#NET "PIO<37>"     LOC = "B14";   # Bank = 0, Pin name = IO_L04P_0, Type = I/O,                        Sch name = R-IO38
#NET "PIO<38>"     LOC = "A16";   # Bank = 0, Pin name = IO_L01N_0, Type = I/O,                        Sch name = R-IO39
#NET "PIO<39>"     LOC = "B16";   # Bank = 0, Pin name = IO_L01P_0, Type = I/O,                        Sch name = R-IO40
 
## 12 pin connectors
##JA
#NET "JA<0>"       LOC = "L15";   # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL,                   Sch name = JA1
#NET "JA<1>"       LOC = "K12";   # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL,       Sch name = JA2
#NET "JA<2>"       LOC = "L17";   # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF,                Sch name = JA3
#NET "JA<3>"       LOC = "M15";   # Bank = 1, Pin name = IO_L07P_1, Type = I/O,                        Sch name = JA4
#NET "JA<4>"       LOC = "K13";   # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL,      Sch name = JA7
#NET "JA<5>"       LOC = "L16";   # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL,                   Sch name = JA8
#NET "JA<6>"       LOC = "M14";   # Bank = 1, Pin name = IO_L05P_1, Type = I/O,                        Sch name = JA9
#NET "JA<7>"       LOC = "M16";   # Bank = 1, Pin name = IO_L07N_1, Type = I/O,                        Sch name = JA10
 
##JB
#NET "JB<0>"       LOC = "M13";   # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF,                Sch name = JB1
#NET "JB<1>"       LOC = "R18";   # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL,                   Sch name = JB2
#NET "JB<2>"       LOC = "R15";   # Bank = 1, Pin name = IO_L03P_1, Type = I/O,                        Sch name = JB3
#NET "JB<3>"       LOC = "T17";   # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL,                   Sch name = JB4
#NET "JB<4>"       LOC = "P17";   # Bank = 1, Pin name = IO_L06P_1, Type = I/O,                        Sch name = JB7
#NET "JB<5>"       LOC = "R16";   # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF,                Sch name = JB8
#NET "JB<6>"       LOC = "T18";   # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL,                   Sch name = JB9
#NET "JB<7>"       LOC = "U18";   # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL,                   Sch name = JB10
 
##JC
#NET "JC<0>"       LOC = "G15";   # Bank = 1, Pin name = IO_L18P_1, Type = I/O,                        Sch name = JC1
#NET "JC<1>"       LOC = "J16";   # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL,       Sch name = JC2
#NET "JC<2>"       LOC = "G13";   # Bank = 1, Pin name = IO_L20N_1, Type = I/O,                        Sch name = JC3
#NET "JC<3>"       LOC = "H16";   # Bank = 1, Pin name = IO_L16P_1, Type = I/O,                        Sch name = JC4
#NET "JC<4>"       LOC = "H15";   # Bank = 1, Pin name = IO_L17N_1, Type = I/O,                        Sch name = JC7
#NET "JC<5>"       LOC = "F14";   # Bank = 1, Pin name = IO_L21N_1, Type = I/O,                        Sch name = JC8
#NET "JC<6>"       LOC = "G16";   # Bank = 1, Pin name = IO_L18N_1, Type = I/O,                        Sch name = JC9
#NET "JC<7>"       LOC = "J12";   # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL,                    Sch name = JC10
 
##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
#NET "JD<0>"       LOC = "J13";   # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL,                    Sch name = JD1
#NET "JD<1>"       LOC = "M18";   # Bank = 1, Pin name = IO_L08N_1, Type = I/O,                        Sch name = JD2
#NET "JD<2>"       LOC = "N18";   # Bank = 1, Pin name = IO_L08P_1, Type = I/O,                        Sch name = JD3
#NET "JD<3>"       LOC = "P18";   # Bank = 1, Pin name = IO_L06N_1, Type = I/O,                        Sch name = JD4
 
## RS232 connector
#NET "RsRx"        LOC = "U6";    # Bank = 2, Pin name = IP, Type = INPUT,                             Sch name = RS-RX
#NET "RsTx"        LOC = "P9";    # Bank = 2, Pin name = IO, Type = I/O,                               Sch name = RS-TX

Integrantes

Carlos David Escobar
Jean Peare Rubio
Carlos Castellanos

1 «Pong». Killer List of Videogames. Consultado el 22 de octubre de 2008.

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